Stress Test Program for Xilinx FPGA

We are seeking a talented, self-driven and motivated software engineer/FPGA designer/engineer to support the development of a test to prove out the reliability of space-bound FPGA designs. The applicant must be proficient in Xilinx Vivado and ISE suites (specifically ISE WebPack design software from Xilinx) and technically confident to develop code while working independently. The objective of this contract is to develop an FPGA level software routine similar to an iterative Built-In-Self-Test (BIST) to be used in an environment-based accelerated test of the Artix-7 evaluation board (AC701). The program will utilize logic and memory within the FPGA (nothing too complex - think basic IO, some math and some memory stores, iterations and output to a file). Applicant should be proficient in VHDL coding and/or Verilog, knowledge of common IO and memory addressing techniques, with the ability to generate an output file and basic API for monitoring the BIST's progress. Development using C/C++ is recommended but not required.