Code a CNN in Verilog for detecting digits from MNIST Database

I need a working code in Verilog that is able to successfully simulate, synthesize and generate bitstream on Xilinx Vivado for FPGA. The code should be able to implement a Convolutional Neural Network and take as input weights and biases from a pretrained model in Python and then use them to identify the 28x28 pixel test image from a MNIST database. Whatever digit is identified by the code, relevant LED on the FPGA board should light up. For eg if the digit identified is a 2, then 2nd LED on the board should light up.

The code should contain a testbench file for simulating the results. The CNN may have once layer of Convolution, one layer of max pool, two hidden layers and one output layers.