ADC configuration in Verilog for SDR on FPGA Zynq

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  • #2635267
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Tauqeer K.Ayyaz G.Kartik P.Calvin I. have already sent a proposal.
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Description

Experience Level: Intermediate
We are working on Software Defined Radio .For the Receiver portion we need an ADC to connect RF signal with Digital Front End.
IF is 455KHz.
Sample is of 16Bits.
Signal Level from RF Team at input will be 0dBm.

Check the ADC in RX portion in the attachment.

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