Looking to interface DDR3 memory to 7 series (Artix 7) FPGA in VHDL using MIG
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I need to interface DDR3 memory to Artix 7 FPGA using MIG ip core. I use a 2 channel 13 bit ADC as input source.
I am working on AC701 evaluation board. As the ADC AD9613 is 2 channel output(Ch A, Ch B) i want to write the data
in DDR3 memory and read the data back when ever i want to read. I want to use chipscope as a debug tool to check whether the data is correct or not.
I am working on AC701 evaluation board. As the ADC AD9613 is 2 channel output(Ch A, Ch B) i want to write the data
in DDR3 memory and read the data back when ever i want to read. I want to use chipscope as a debug tool to check whether the data is correct or not.
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