Edit my RISC V core

Seeking an experienced engineer to modify a RISC-V core for integration into my electronic system. Tasks include correcting current implementation issues, optimizing pipeline and control logic, implementing requested ISA extensions, and ensuring timing closure for target FPGA/ASIC. Deliverables: updated RTL with clear, annotated changes, simulation testbenches, synthesis constraints, and documentation of modifications and verification results. Candidates must demonstrate prior RISC-V core experience, provide estimates for timeline and cost, and ensure deliverables are production-ready.