Processor design using vhdl

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Naam S.Ian Y. have already sent a proposal.
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Description

Experience Level: Expert
I have to design and implement a multithreading processor on a fpga.

Note:
I have already taken a simple processor and VHDL coding is done such that it implements various instructions(operations). So, i need only small modifications to be done in the code such that it implements multithreading and each thread executes only one instruction at a time. I also need the coding such that it is port mapped to the Xilinx virtex II pro XC2VP30 fpga because i have a kit already given to me so that i can implement on that.

NOTE: I need it within 3-4 days. Since most of the work is done and it needs only slight modifications to implement multithreading as per given conditions below.

I have given details of my project below:
My project is to design a Barrel processor (architecture design and coding in VHDL). I have given a short note on my project below.

The processor has to execute one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the processor and has to implement the processor on a FPGA by using VHDL.

So, I have to take a basic architecture( I have already taken a architecture and coding is done so only modifications have to be made ) and have to modify it such that the processor has N - number of PC,Add reg,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time.

For example Thread -1 is taken and all its corresponding CPU registers are loaded, then one instruction from this thread is executed. Then again Thread -2 is taken and all its CPU registers are loaded, then one instruction from this thread is executed, etc. upto N threads and again its cycled from the first.

Example:
Thread -1 Ro-Rn PC1 Addreg1 Thread ID Flags Thread-status(En/Disable)
Thread -2 Ro-Rn PC2 Addreg2 Thread ID Flags Thread-status(En/Disable)
Thread -3 Ro-Rn PC3 Addreg3 Thread ID Flags Thread-status(En/Disable)

So, I have to design an architecture and then i have to code in VHDL.
I ll send the code once my job is awared.

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