Digital Design using VHDL
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- Proposals: 2
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- #1647906
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Description
Experience Level: Expert
General information for the business: Digital Design
Description of support work: 4. Report
The deliverables for this report are listed below. Your report should include,
• A block diagram of the entire design.
• A description of the signals between the blocks of the block diagram.
• A description of your test strategy using VHDL test benches (Not using Do file or scripts), all the VHDL Coding needs to be in appendix with the comments).
• The VHDL code for the design.
• The simulation results (i.e. output file) of the verification.
Furthermore, the report should contain an introduction and conclusion. Simulation results should be presented in a readable and sensible format.
Extra notes: 4. Report
The deliverables for this report are listed below. Your report should include,
• A block diagram of the entire design.
• A description of the signals between the blocks of the block diagram.
• A description of your test strategy using VHDL test benches (Not using Do file or scripts), all the VHDL Coding needs to be in appendix with the comments).
• The VHDL code for the design.
• The simulation results (i.e. output file) of the verification.
Furthermore, the report should contain an introduction and conclusion. Simulation results should be presented in a readable and sensible format.
Description of support work: 4. Report
The deliverables for this report are listed below. Your report should include,
• A block diagram of the entire design.
• A description of the signals between the blocks of the block diagram.
• A description of your test strategy using VHDL test benches (Not using Do file or scripts), all the VHDL Coding needs to be in appendix with the comments).
• The VHDL code for the design.
• The simulation results (i.e. output file) of the verification.
Furthermore, the report should contain an introduction and conclusion. Simulation results should be presented in a readable and sensible format.
Extra notes: 4. Report
The deliverables for this report are listed below. Your report should include,
• A block diagram of the entire design.
• A description of the signals between the blocks of the block diagram.
• A description of your test strategy using VHDL test benches (Not using Do file or scripts), all the VHDL Coding needs to be in appendix with the comments).
• The VHDL code for the design.
• The simulation results (i.e. output file) of the verification.
Furthermore, the report should contain an introduction and conclusion. Simulation results should be presented in a readable and sensible format.
Hashim G.
100% (47)Projects Completed
45
Freelancers worked with
25
Projects awarded
53%
Last project
9 May 2019
United Arab Emirates
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Dear Hashim G.,
Thank you for your invitation.
I am a Structural engineer, so I cannot help you with this situation.
Best of all,
Krisztian Loki
464714
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